Summary: Processors are the
actual working part of a computer, performing arithemetic, logic, and other
operations needed to run computer programs.
- processors
- CISC
- RISC
- DSP
- Hybrid
A computer is a programmable
machine. There are two basic kinds of computers: analog and digital.
Analog computers are analog devices.
That is, they have continuous states rather than discrete numbered states. An
analog computer can represent fractional or irrational values exactly, with no
round-off. Analog computers are almost never used outside of experimental
settings.
A digital computer is a
programmable clocked sequential state machine. A digital computer uses discrete
states. A binary digital computer uses two discrete states, such as
positive/negative, high/low, on/off, used to represent the binary digits zero
and one.
The classic crude oversimplication of a
computer is that it contains three elements: processor unit, memory, and I/O
(input/output). The borders between those three terms are highly ambigious,
non-contiguous, and erratically shifting.
processors
The
processor is the part of the computer that actually does the
computations. This is sometimes called an MPU (for main processor unit)
or CPU (for central processing unit or central processor unit).
A
processor typically contains an arithmetic/logic unit (ALU), control
unit (including processor flags, flag register, or status register), internal
buses, and sometimes special function units (the most common special function
unit being a floating point unit for floating point arithmetic).
Some
computers have more than one processor. This is called multi-processing.
The
major kinds of digital processors are: CISC, RISC, DSP, and hybrid.
CISC
CISC stands for Complex Instruction Set
Computer. Mainframe computers and minicomputers were CISC processors, with
manufacturers competing to offer the most useful instruction sets. Many of the
first two generations of microprocessors were also CISC.
“In
many computer applications, programs written in assembly language exhibit the
shortest execution times. Assembly language programmers often know the computer
architecture more intimately, and can write more efficient programs than
compilers can generate from high level language (HLL) code. The disadvantage of
this method of increasing program performance is the diverging cost of computer
hardware and software. On one hand, it is now possible to constrcut an entire
computer on a single chip of semiconductor material, its cost being very small
compared to the cost of a programmer’s time. On the other hand, assembly
language programming is perhaps the most time-consuming method of writing
software.
“One
way to decrease software costs is to provide assembly language instructions
that perform complex tasks similar to those existing in HLLs. These tasks, such
as the character select
instruction, can be executed in one powerful assembly language instruction. A
result of this philosophy is that computer instruction sets become relatively
large, with many complex, special purpose, and often slow instructions. Another
way to decrease software costs is to program in a HLL, and then let a compiler
translate the program into assembly language. This method does not always
produce the most efficient code. It has been found that it is extremely
difficult to write an efficient optimizing compiler for a computer that has a
very large instruction set.
“How
can the HLL program execute more quickly? One approach is to narrow the
semantic distance between the HLL concepts and the underlying architectual
concepts. This closing of the semantic gap supports lower software costs, since
the computer more closely matches the HLL, and is therefore easier to program
in an HLL.
“As
instruction sets become more complex, significant increases in performance and
efficiency occurred.”
RISC
RISC stands for Reduced Instruction Set
Computer. RISC came about as a result of academic research that showed that a
small well designed instruction set running compiled programs at high speed
could perform more computing work than a CISC running the same programs
(although very expensive hand optimized assembly language favored CISC).
“Some
designers began to question whether computers with complex instruction sets are
as fast as they could be, having in mind the capabilities of the underlying
technology. A few designers hypothesized that increased performance should be
possible through a streamlined design, and instruction set simplicity. Thus,
research efforts began in order to investigate how processing performance could
be increased through simplified architectures. This is the root of the reduced
instruction set computer (RISC) design philosophy.
“Seymour
Cray has been credited with some of the very early RISC concepts. In an effort
to design a very high speed vector processor (CDC 6600), a simple instruction
set with pipelined execution was chosen. The CDC 6600 computer was register
based, and all operations used data from registers local to the arithmetic
units. Cray realized that all operations must be simplified for maximal
performance. One complication or bottleneck in processing can cause all other
operations to have degraded performance.
“Starting
in the mid 1970s, the IBM 801 research team investigated the effect of a small
instruction set and optimizing compiler design on computer performance. They
performed dynamic studies of the frequency of use of different instructions in
actual application programs. In these studies, they found that approximately 20
percent of the available instructions were used 80 percent of the time. Also,
complexity of the control unit necessary to support rarely used instructions,
slows the execution of all instructions. Thus, through careful study of program
characteristics, one can specify a smaller instruction set consisting only of
instructions which are used most of the time, and execute quickly.
“The
first major university RISC research project was at the University of
California, Berkeley (UCB), David Patterson, Carlos Séquin, and a group of
graduate students investigated the effective use of VSLI in microprocessor
design. To fit a powerful processor on a single chip of silicon, they looked at
ways to simplify the processor design. Much of the circuitry of a modern
computer CPU is dedicated to the decoding of instructions and to controlling
their execution. Microprogrammed CISC computers typically dedicate over half of
their circuitry to the control section. However, UCB researchers realized that
a small instruction set requires a smaller area for control circuitry, and the
area saved could be used by other CPU functions to boost performance. Extensive
studies of application programs were performed to determine what kind of
instructions are typically used, how often they execute, and what kind of CPU
resources are needed to support them. These studies indicated that a large
register set enhanced performance, and pointed to specific instruction classes
that should be optimized for better performance. The UCB research effort
produced two RISC designs that are widely referenced in the literature. These
two processors developed at UCB can be referred to as UCB-RISC I and UCB-RISC
II. The mnemonics RISC and CISC emerged at this time.
“Shortly
after the UCB group began its work, researchers at Stanford University (SU),
under the direction of John Hennessy, began looking into the relationship
between computers and compilers. Their research evolved into the design and
implementation of optimizing compilers, and single-cycle instruction sets.
Since this research pointed to the need for single-cycle instruction sets,
issues related to complex, deep pipelines were also investigated. This research
resulted in a RISC processor for VSLI that can be referred to as the SU-MIPS.
“The
result of these initial investigations was the establishment of a design
philosophy for a new type of von Neumann architecture computer. Reduced
instruction set computer design resulted in computers that execute instructions
faster than other computers built of the same technology. It was seen that a
study of the target application programs is vital in designing the instruction
set and datapath. Also, it was made evident that all facets of a computer
design must be considered together.
“The
design of reduced instruction set computers does not rely upon inclusion of a
set of required features, but rather, is guided by a design philosophy. Since
there is no strict definition of what constitutes a RISC design, a significant
controversy exists in categorizing a computer as RISC or CISC.
“The
RISC philosophy can be stated as follows: The effective speed of a computer can be maximized by migrating all but
the most frequently used functions into software, thereby simplifying the
hardware, and allowing it to be faster. Therefore, included in hardware are
only those performance features that are pointed to by dynamic studies of HLL
programs. The same philosophy applies to the instruction set design, as well as
to the design of all other on-chip resources. Thus, a resource is incorporated
in the architecture only if its incorporation is justified by its frequency of
use, as seen from the language studies, and if its incorporation does not slow down
other resources that are more frequently used.
“Common
features of this design philsophy can be observed in several examples of RISC
design. The instruction set is based upon a load/store approach. Only load and store instructions access memory. No arithmetic, logic, or I/O
instruction operates directly on memory contents. This is the key to
single-cycle execution of instructions. Operations on register contents are
always faster than operations on memory contents (memory references usually
take multiple cycles; however, references to cached or buffered operands may be
as rapid as register references, if the desired operand is in the cache, and
the cache is on the CPU chip). Simple instructions and simple addressing modes
are used. This simplificiation results in an instruction decoder that is small,
fast, and relatively easy to design. It is easier to develop an optimizing
compiler for a small, simple instruction set than for a complex instruction
set. With few addressing modes, it is easier to map instructions onto a
pipeline, since the pipeline can be designed to avoid a number of computation
related conflicts. Little or no microcode is found in many RISC designs. The
absence of microcode implies that there is no complex micro-CPU within the instruction
decode/control section of a CPU. Pipelining is used in all RISC designs to
provide simultaneous execution of multiple instructions. The depth of the
pipeline (number of stages) depends upon how execution tasks are subdivided,
and the time required for each stage to perform its operation. A carefully
designed memory hierarchy is required for increased processing speed. This
hierarchy permits fetching of instructions and operands at a rate that is high
enough to prevent pipeline stalls. A typical hierarchy includes high-speed
registers, cache, and/or buffers located on the CPU chip, and complex memory
management schemes to support off-chip cache and memory devices. Most RISC
designs include an optimizing compiler as an integral part of the computer architecture.
The compiler provides an interface between the HLL and the machine language.
Optimizing compilers provide a mechanism to prevent or reduce the number of
pipeline faults by reorganizing code. The reorganization part of many compilers
moves code around to eliminate redundant or useless statements, and to present
instructions to the pipeline in the most efficient order. All instructions
typically execute in the minimum possible number of CPU cycles. In some RISC
designs, only load/store instructions require more than one cycle in which to
execute. If all instructions take the same amount of time, the pipeline can be
designed to recover from faults more easily, and it is easier for the compiler
to reorganize and optimize the instruction sequence.”
DSP
DSP stands for Digital Signal
Processing. DSP is used primarily in dedicated devices, such as MODEMs, digital
cameras, graphics cards, and other specialty devices.
Hybrid
Hybrid processors combine elements of two
or three of the major classes of processors.